Biosketch

Dr. Kunwar Singh received his B. Tech. in Electronics and Communication Engineering from Guru Tegh Bahadur Institute of Technology, GGSIP University, New Delhi and M. Tech. in VLSI Design from Centre for Development of Advanced Computing (CDAC), Noida in 2006 and 2009 respectively. He was awarded Ph.D. degree from Department of Electronics & Communication Engineering, University of Delhi in 2016. He worked as an intern in Cadence Design Systems during Feb. 2009 – Jul. 2009 in Silicon Package Board group. He is currently serving as an Assistant Professor in the Department of ECE, Netaji Subhas University of Technology (erstwhile Netaji Subhas Institute of Technology) wef Sep. 2013. Earlier, he has also served as Assistant Professor in the Department of Electrical Engineering, Delhi Technological University (Erstwhile Delhi College of Engineering) from Jul. 2010 – Sep. 2013. His research interests include Applications of AI techniques in automated performance optimization of CMOS circuits, AI driven EDA/CAD flows for VLSI Design, Design of low power and high performance digital CMOS circuits, CMOS-memristor hybrid circuits, Neuromorphic Computing. He has authored and co-authored more than 25 research articles in the above areas in various international/national journals and conferences. He has filed one patent application in Indian Patent Office. He is a member of Circuits & Systems society of IEEE.

Selected Publications:

a. Gurjit Singh Walia, Kartik Aggarwal, Kuldeep Singh, Kunwar Singh, “Design and Analysis of Adaptive Graph based Cancelable Multi-biometrics Approach” IEEE Transactions on Dependable and Secure Computing, (Accepted for publication, May 2020) Doi: 10.1109/TDSC.2020.2997558

b .Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta,” A Closed Loop ASIC Design Approach based on Logical Effort Theory and Artificial Neural Networks”, Integration, The VLSI Journal, Elsevier, volume 69, pages 10-22, 2019.

c. Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta, “Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms” Integration, The VLSI Journal, Elsevier, volume 60, pages 25-38, 2018.

Areas of Interest

1. Applications of AI techniques for automated performance optimization of digital and analog CMOS circuits

2. AI driven EDA/CAD flows for VLSI Design

3. Design of low power and high performance digital CMOS circuits

4. CMOS-memristor hybrid circuits

5. Neuromorphic computing

Publications in International Journal

 

Publications in National Journal

 

Publications in National Conferences

 

Publications in International Conferences

 

Books/Book Chapters

 

Publications (Click to expand)

Patents filed: 

1. Title: Method and system for automated design of an integrated circuit using configurable cells. (Filed in Indian Patent Office)

Application No. 3282/DEL/2012                     URL: https://urlzs.com/2xtq3

Filed on: 25th Oct. 2012                                   Status: Pending

International Journals:

1. G. S. Walia, K. Aggarwal, K. Singh and K. Singh, "Design and Analysis of Adaptive Graph based Cancelable Multi-Biometrics Approach," in IEEE Transactions on Dependable and Secure Computing,  doi: 10.1109/TDSC.2020.2997558. May 2020.

2. P. Kumar, M. Gupta, & K. Singh, “Performance Analysis of Charge Plasma Based Five Layered Black Phosphorus-Silicon Heterostructure Tunnel Field Effect Transistor” Silicon, Springer, 2020. https://doi.org/10.1007/s12633-020-00376-7

3. P. Kumar, M. Gupta, & K. Singh, “Performance Evaluation of Transition Metal Dichalcogenides based Steep Subthreshold Slope Tunnel Field Effect Transistor” Silicon, Springer, vol. 12, no. 8, pp. 1857–1864, 2019. https://doi.org/10.1007/s12633-019-00285-4.

4. K. Singh, S. C. Tiwari and M. Gupta, “A Closed Loop ASIC Design Approach based on Logical Effort Theory and Artificial Neural Networks”, Integration: The VLSI Journal, Elsevier, volume 69, pages 10-22, 2019.

5. K. Singh, A. Jain, A. Mittal, V. Yadav, A. A. Singh, A. K. Jain and M. Gupta, “Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms”, Integration: The VLSI Journal, Elsevier, volume 60, pages 25-38, 2018. (This paper was amongst the most downloaded articles of the journal for the year 2018 and even achieved  2nd  rank during May 2018)

6. G. S. Walia, S. Makhija, K. Sharma and K. Singh, “Robust Stego-Key Directed LSB Substitution Scheme based upon Cuckoo Search and Chaotic Map”, Optik - International Journal for Light and Electron Optics, Elsevier, volume 170, pages 106-124, 2018.

Book Chapter:

1. K. Singh, S. C. Tiwari and M. Gupta, In book: Design and Modeling of Low Power VLSI Systems, Edition: First, Chapter: State-of-the-Art Master Slave Flip-Flop Designs for Low Power VLSI Systems, Publisher: IGI Global, USA, 2016, pp. 166-198.

International Conferences:

1. P. Kumar, M. Gupta and K. Singh, "Low Leakage Current Molybdenum Ditelluride based nano FET using Non-Equilibrium Green’s Function," 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India, 2020, pp. 797-799, doi: 10.1109/SPIN48934.2020.9070986.

2. A. Tripathi, V. Yadav and K. Singh, “Performance Comparison between Single Solution and Population based Heuristics for Optimal Gate Sizing of CMOS Digital Integrated Circuits, “ 2019 International Conference on Energy, Environment & Material Sciences (ICE2M), Gorakhpur, India. (Accepted for publication) 

3. T. K. Yadav and K. Singh, "Performance Optimization of OTA Using PSO Guided by Inversion Coefficient Theory," 2019 International Conference on Information and Digital Technologies (IDT), Zilina, Slovakia, 2019, pp. 266-270, doi: 10.1109/DT.2019.8813351.

4. P. Kumar, M. Gupta and K. Singh, “Analysis of Transition Metal Dichalcogenide Materials Based Nanotube”, 2019 International Conference on Emerging Trends in Electro-Mechanical Technologies and Management (TEMT), New Delhi, India, 2019 (Accepted for publication)

5. N. Pandey and K. Singh, "Automated Transistor Sizing of Digital Integrated Circuits using LE theory and Firefly Algorithm," 2019 International Conference on Computing, Power and Communication Technologies (GUCON), NCR New Delhi, India, 2019, pp. 605-610.

6. R. Kukreti and K. Singh, "Performance Optimization of Digital CMOS Integrated Circuits using LE Theory and APSO," 2019 International Conference on Computing, Power and Communication Technologies (GUCON), NCR New Delhi, India, 2019, pp. 600-604.

7. A. Anand, B. Aggarwal and K. Singh, "Memristor Based Oscillator," 2019 International Conference on Computing, Power and Communication Technologies (GUCON), NCR New Delhi, India, 2019, pp. 89-92.

8. P. Kumar, M. Gupta and K. Singh,” Study of static properties of two dimensional (2-D) materials” 2019 International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE), New Delhi, India, 2019 (Accepted for publication)

9. P. Kumar and K. Singh, "Implementation of High Performance Clock-gated Flip-flops," 2018 2nd IEEE International Conference on Power Electronics, Intelligent Control and Energy Systems (ICPEICES), Delhi, India, 2018, pp. 1032-1035, doi: 10.1109/ICPEICES.2018.8897339.

10. A. Sharma, K. Singh and P. S. Khurana, "A Low Power Hybrid CMOS-Memristor based Ring Oscillator for Hardware Security Applications," 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2018, pp. 117-120, doi: 10.1109/RTEICT42901.2018.9012091.

11. P. S. Khurana, K. Singh and A. Sharma, "A Hybrid CMOS-Memristor based Programmable Wien Bridge Oscillator," 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, 2018, pp. 2207-2210, doi: 10.1109/RTEICT42901.2018.9012638.

12. A. Goswami, M. Agarwal, T. K. Rawat and K. Singh, "FPGA implementation of reconfigurable architecture for half-band FIR filters," 2017 4th International Conference on Signal Processing, Computing and Control (ISPCC), Solan, 2017, pp. 592-596 

13. S. C. Tiwari, M. A. Khan, K. Singh, A. Sangal, "Standard Test Bench for Optimization and characterization of Combinational Circuits”, 2012 IEEE International Conference on Signal Processing, Computer and Control, Solan, India, 2012 pp. 1-5.  

14. K. Singh, S. C. Tiwari and M Gupta, “A High Performance Flip-flop for Low Power Low Voltage Systems” 2011 World Congress on Information and Communication Technologies, Mumbai, 2011, pp. 257-262. 

15. S. C. Tiwari, K. Singh and M. Gupta, “Design and Development of Circuit Optimizer using Tcl and SpectreMDL(SPICE) Interface” 2011 World Congress on Information and Communication Technologies, Mumbai, 2011, pp. 1385-1389. 

16. S. C. Tiwari, K. Singh and M. Gupta, “Logical Effort based automated Transistor Width Optimization Methodology” 2011 World Congress on Information and Communication Technologies, Mumbai, 2011, pp. 1067-1072.

17. S. C. Tiwari, K. Singh and M. Gupta, “A Novel Methodology for Flip-flop Optimization and Characterization in the NoC Design Space” 2011 World Congress on Information and Communication Technologies, Mumbai, 2011, pp. 251-256. 

18. S. C. Tiwari, K. Singh and M. Gupta "A Low Power High Density Double Edge Triggered Flip-flop for Low Voltage Systems," 2010 International Conference On Advances in Recent Technologies in Communication and Computing (ARTCOM), Kottayam, 2010, pp. 377-380.

19. M. Sharma, A. Noor, S. C. Tiwari and K. Singh, "An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop," 2009 International Conference on Advances in Recent Technologies in Communication and Computing (ARTCOM), Kottayam, 2009, pp. 478-481.